hy5118164c,hy5116164c 1mx16, extended data out mode this family is a 16m bit dynamic ram organized 1,048,576 x 16-bit configuration with extended data out mode cmos drams . extended data out mode is a kind of page mode which is useful for the read operation. the circuit and process design allow this device to achieve high performance and low power dissipation. optional features are access time(60, 70 or 80ns) and refresh cycle(1k ref. or 4k ref.) and power consumption (normal or low power with self refresh). hyundai ? s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. description features ? extended data out operation ? read-modify-write capability ? ttl compatible inputs and outputs ? /cas-before-/ras, /ras-only, hidden and self refresh capability ? max. active power dissipation speed 60 1 k refresh 880 mw 4 k refresh 550 mw ? fast access time and cycle time speed 60 70 trac 60 ns 70 ns tcac 15 ns 20 ns thpc 25 ns 30 ns ? refresh cycle part number hy5118164c hy5116164c refresh 1 k 4 k normal 16 ms sl-part 256 ms this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licences are implied rev.00 / sep.97 ordering information part name hy5118164cjc refresh 1 k power package 42 pin soj hy5118164csljc 1 k sl-part 42 pin soj hy5118164ctc 1 k 44/50 pin tsop-ii hy5118164csltc 1 k sl-part hy5116164cjc 4 k 42 pin soj hy5116164csljc 4 k sl-part 70 825 mw 495 mw hyundai semiconductor ? jedec standard pinout ? 42-pin plastic soj (400mil) 44/50-pin plastic tsop-ii (400mil) ? single power supply of 5v 10% ? early write or output enable controlled write 1 * sl : low power with self refresh 64 ms hy5116164ctc 4 k hy5116164csltc 4 k sl-part 44/50 pin tsop-ii 80 770 mw 440 mw 80 80 ns 20 ns 35 ns 44/50 pin tsop-ii 44/50 pin tsop-ii 42 pin soj
hy5118164c,hy5116164c functional block diagram we lcas ucas oe data input buffer dq0~7 dq8~15 data output buffer dq0~7 dq8~15 cas clock generator cloumn predecoder (10/8)* refresh controller refresh counter (10/12)* cas clock generator sense amp i/o gate memory array 4,194,304x16 row decoder ras clock generator substrate bias generator v cc v ss address buffer ras dq0 ~ dq15 *( a10) and *(a11) for 4k refresh part (1 k refresh / 4k refresh)* (10/8)* (10/12)* 8 8 8 8 8 8 8 8 a0 a1 *( a10) *( a11) a9 a2 ~ 2 1 mx16,edo dram rev.00 / sep.97
hy5116164c,hy5116164c pin configuration (marking side) pin description / ras / cas row address strobe column address strobe / we write enable / oe output enable a0~a11 address input (4k refresh product) a0~a9 address input (1k refresh product) dq0~dq15 data in/out vcc power (5v) vss ground nc no connection 44/50 pin plastic tsop- ii (400mil) pin name parameter 3 1 mx16,edo dram rev.00 / sep.97 42 pin plastic soj (400mil) *( n.c) : for 1k refresh product
hy5118164c,hy5116164c absolute maximum rating symbol t a parameter ambient temperature rating 0 to 70 unit c t stg storage temperature -55 to 150 c v in, v out voltage on any pin relative to v ss -1.0 to 7.0 v v cc voltage on v cc relative to v ss -1.0 to 7.0 v i os short circuit output current 50 ma p d power dissipation 1 w t solder soldering temperature ? time 260 ? 10 c ? sec note : operation at or above absolute maximum ratings can adversely affect device reliability symbol i li parameter input leakage current (any input) unit m a min -10 max 10 test condition v ss v in v cc + 1.0 all other pins not under test = v ss dc operating characteristic i lo output leakage current (any input) m a -10 10 v ss v out v cc /ras & /cas at v ih v ol output low voltage v - 0.4 i ol = 4.2 ma v oh output high voltage v 2.4 - i oh = -5.0 ma 4 recommended dc operating conditions symbol v cc parameter power supply voltage unit v max 5.5 typ 5.0 min 4.5 v ih input high voltage v v cc+ 1.0 - 2.4 v il input low voltage v 0.8 - -1.0 note : all voltages are referenced to v ss . ( t a = 0 c to 70 c ) 1 mx16,edo dram rev.00 / sep.97
hy5118164c,hy5116164c dc characteristics symbol i cc1 parameter operating current speed 60 70 80 unit ma ( t a = 0 c to 70 c , v cc = 5v 10% , v ss = 0v, unless otherwise noted.) note 1 k ref 160 150 140 4 k ref 100 90 80 test condition / ras, /cas cycling t rc = t rc (min.) max. current i cc2 ttl standby current ma 2 1 2 1 / ras, /cas 3 v ih other inputs 3 v ss i cc3 / ras-only refresh current 60 70 80 ma 160 150 140 100 90 80 / ras cycling,/cas = v ih t rc = t rc (min.) i cc4 edo mode current 60 70 80 ma 140 120 100 120 100 80 / cas cycling, /ras = v il t hpc = t hpc (min.) i cc5 cmos standby current sl-part ma m a 1 200 1 200 / ras = /cas 3 v cc - 0.2v i cc6 / cas-before-/ras refresh current 60 70 80 ma 160 150 140 100 90 80 / ras & /cas = 0.2v t rc = t rc (min.) i cc7 battery back-up current (sl-part) m a 350 trc =250 s (1k ref), 62.5 s (4k ref) /cas = 0.2v /oe & /we = v cc - 0.2v address = vcc -0.2v or 0.2v dq0~dq15 = vcc -0.2, 0.2v or open i cc8 self refresh current (sl-part) m a 350 350 / ras & /cas = 0.2v other pins are same as i cc7 1. i cc1 , i cc3 , i cc4 and i cc6 depend on output loading and cycle rates( t rc and t hpc ). 2. specified values are obtained with output unloaded. 3. i cc is specified as an average current. in i cc1 , i cc3 , i cc6 , address can be changed only once while /ras=v il . in i cc4 , address can be changed maximum once while /cas=v ih within one edo mode cycle time t hpc . 5 sl-part 1 mx16,edo dram rev.00 / sep.97 tras 300ns tras 1 s 450 350 450
t rc random read or write cycle time 105 ns symbol parameter min max min max unit note 60 ns 70 ns ac characteristics ( t a = 0 c to 70 c , v cc = 5 v 10% , v ss = 0v, unless otherwise noted.) hy5118164c,hy5116164c read-modify-write cycle time 142 edo mode cycle time 25 edo mode read-modify-write cycle time 73 access time from /ras - access time from /cas - access time from column address - access time from /cas precharge - / cas to output low impedance output buffer turn-off delay from /cas transition time(rise and fall) / ras precharge time / ras pulse width / ras pulse width(edo mode) / ras hold time / cas hold time / cas pulse width / ras to /cas delay time / ras to column address delay time / cas to /ras precharge time / cas precharge time row address set-up time row address hold time column address set-up time column address hold time column address to /ras lead time read command set-up time read command hold time referenced to /cas t rwc t hpc t hprwc t rac t cac t aa t cpa t clz t cez t t t rp t ras t rasp t rsh t csh t cas t rcd t rad t crp t cp t asr t rah t asc t cah t ral t rcs t rch 0 3 3 40 60 60 13 40 13 20 15 5 7 0 10 0 10 30 0 0 - - - - 60 15 30 35 - 15 50 - 10 k 100 k - - 10 k 45 30 - - - - - - - - - 125 167 30 85 - - - - 0 3 3 50 70 70 15 50 15 20 15 5 10 0 10 0 15 35 0 0 - - - - 70 20 35 35 - 15 50 - 10 k 100 k - - 10 k 50 35 - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 2 2 5,6,7 5,6 5 5 5 8,12 3 6 7 11 16 9 1 mx16,edo dram rev.00 / sep.97 read command hold time referenced to /ras t rrh 0 - 0 - ns 9 write command hold time write command pulse width t wch t wp 10 10 - - 15 10 - - ns ns write command to /ras lead time t rwl 15 - 15 - ns t cwl write command to /cas lead time ns 13 - 15 - 16 min max 80 ns 145 187 35 100 - - - - 0 3 3 60 80 80 20 60 20 20 15 5 10 0 10 0 15 40 0 0 - - - - 80 20 40 40 - 15 50 - 10 k 100 k - - 10 k 60 40 - - - - - - - - - 0 - 15 10 - - 15 - 20 -
symbol parameter min max min max unit note 60 ns 70 ns ac characteristics continued hy5118164c,hy5116164c data-in set-up time data-in hold time refresh period(1024 cycles) refresh period(4096 cycles) refresh period(sl-part) write command set-up time / cas to /we delay time / ras to /we delay time column address to /we delay time / cas set-up time(cbr cycle) / cas hold time(cbr cycle) / ras to /cas precharge time / cas precharge time(cbr counter test) / ras hold time referenced to /oe / oe access time / oe to data delay time output buffer turn-off delay time from /oe / oe command hold time / we delay time from /cas precharge / ras hold time from /cas precharge / we to /ras precharge time(cbr cycle) / we to /ras hold time(cbr cycle) / ras pulse width(self refresh) t ds t dh t ref t wcs t cwd t rwd t awd t csr t chr t rpc t cpt t roh t oea t oed t oez t oeh t cpwd t rhcp t wrp t wrh t rass 0 10 - - - 0 37 80 50 5 10 5 30 10 - 15 3 15 55 40 10 10 100 k - - 16 64 256 - - - - - - - - - 15 - 15 - - - - - - 0 15 - - - 0 45 95 60 5 10 5 35 10 - 20 3 20 65 40 10 10 100 k - - 16 64 256 - - - - - - - - - 20 - 15 - - - - - - ns ns ms ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 10 10 11 11,15 11 11 17 18 14 8 11 1 mx16,edo dram rev.00 / sep.97 output data hold time output buffer turn off delay time from /ras / we to data delay time / oe precharge time t rps t chs t doh t rez t wez t wed t oep 110 -50 5 3 3 15 5 - - - 15 15 - - 130 -50 5 3 3 15 5 - - - 15 15 - - ns ns ns ns ns ns ns t wpe t och t cho / ras precharge time (self refresh) / cas hold time (self refresh) output buffer turn off delay time from /we / we pulse width (edo cycle) / oe to /cas hold time 5 5 - - 5 5 - - ns ns / cas hold time to /oe 5 - 5 - ns min max 0 15 - - - 0 45 105 65 5 10 5 40 10 - 20 3 20 75 50 10 10 100 k - - 16 64 256 - - - - - - - - - 20 - 15 - - - - - - 150 -50 5 3 3 15 5 - - - 15 15 - - 5 5 - - 5 - 80 ns
hy5118164c,hy5116164c note 1. an initial pause of 200 m s is required after power-up followed by 8 /ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cbr refresh cycles instead of 8 /ras-only refresh cycles are required. 2 t asc 3 t cp (min), assume t t =3ns. 3. vih(min.) and vil(max.) are reference levels for measuring timing of input signals. transition times are measured between vih(min.) and vil(max.) 4. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (ta=0 to 70 ?? c) is assured. 5. measured at v oh =2.0v and vol=0.8v with a load equivalent to 2ttl loads and 100pf. 6. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 7. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 8. t wez , t rez , t cez and t oez define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 9. either t rch or t rrh must be satisfied for a read cycle. 10.these parameters are referenced to /lcas or /ucas leading edge in early write cycles and to /we leading edge in read-modify-write cycles and late write cycle. 11. t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min) , and t cpwd 3 t cpwd (min.) , the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 12.if /ras goes to high before /cas high going,the open circuit condition of the output is achieved by /cas high going. if /cas goes to high before /ras high going,the open circuit condition of the output is achieved by /ras high going. 13. t asc , t cah are referenced to the earlier /cas falling edge. 14. t cp and t cpt are measured when both /lcas and /ucas are high state. 15. t cwd is referenced to the later /cas falling edge at word read- modifiy -write cycle. 16. t cwl must be satisfied by both /lcas and /ucas for 16-bit access cycles. 17. t csr is referenced to the earlier /cas falling before /ras transition low. 18. t chr is referenced to the later /cas rising high after /ras transition low. 19. t ds , t dh is independently specified for lower byte dq(0-7), upper byte dq(8-15). 8 1 mx16,edo dram rev.00 / sep.97 capacitance symbol c in1 parameter input capacitance (a0~a11) max 5 unit pf c in2 input capacitance (/ras, /lcas,/ucas, /we, /oe) 7 pf c dq data input / output capacitance (dq0~dq15) 7 pf ( t a = 25 c, v cc = 5v 10%, v ss = 0v and f=1mhz, unless otherwise noted.) typ . - - -
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